韩杰副教授曾获NanoArch 2015会议最佳论文奖，以及GLSVLSI 2015，NanoArch 2016，ISQED 2018等会议最佳论文提名，其在纳米级容错电路理论方面的研究工作被《Science》期刊关注。韩杰副教授目前担任IEEE Transactions on Emerging Topics in Computing (TETC), IEEE Transactions on Nanotechnology, Microelectronics Reliability期刊副主编，还曾担任DFT 2013，GLSVLSI 2017国际会议主席，以及DFT 2012，GLSVLSI 2016会议技术委员会主席。
Dr. Jie Han received the B.Sc. degree in electronic engineering from Tsinghua University, Beijing, China, in 1999 and the Ph.D. degree from Delft University of Technology, The Netherlands, in 2004. He is currently an Associate Professor in the Department of Electrical and Computer Engineering at the University of Alberta, Edmonton, AB, Canada. His research interests include approximate computing, stochastic computation, reliability and fault tolerance, nanoelectronic circuits and systems, novel computational models for nanoscale and biological applications.
Dr. Han was a recipient of the Best Paper Award at the International Symposium on Nanoscale Architectures (NanoArch 2015) and Best Paper Nominations at the 25th Great Lakes Symposium on VLSI (GLSVLSI 2015), NanoArch 2016 and the 19th International Symposium on Quality Electronic Design (ISQED 2018). He was nominated for the 2006 Christiaan Huygens Prize of Science by the Royal Dutch Academy of Science. His work was recognized by Science, for developing a theory of fault-tolerant nanocircuits (2005).
He is currently an Associate Editor for IEEE Transactions on Emerging Topics in Computing (TETC), IEEE Transactions on Nanotechnology and Microelectronics Reliability. He served as a General Chair for GLSVLSI 2017 and the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2013), and a Technical Program Committee Chair for GLSVLSI 2016 and DFT 2012.
报告题目1: Accurate and Efficient Reliability Evaluation of Logic Circuits
报告时间：2019年2月21日 上午 9:00-11:00
报告摘要：Reliability has become a major concern due to the scaling of CMOS technology into the nanometer regime. Accurate analytical approaches for the reliability evaluation of logic circuits, however, have a computational complexity that increases exponentially with circuit size. It makes the reliability analysis of large circuits intractable. This talk initially presents novel computational models based on stochastic computation; using these stochastic computational models (SCMs), a simulation-based analytical approach is proposed for the reliability evaluation of logic circuits. In this approach, signal probabilities are encoded in the statistics of random binary bit streams and non-Bernoulli sequences of random permutations of binary bits are used for initial input and gate error probabilities. By leveraging the bit-wise dependencies of the random binary streams, the proposed approach takes into account signal correlations and evaluates the joint reliability of multiple outputs. Therefore, it accurately determines the reliability of a circuit; its precision is only limited by the random fluctuations inherent in the stochastic sequences. Based on both simulation and analysis, the SCM approach takes advantages of ease in implementation and accuracy in evaluation. The use of non-Bernoulli sequences as initial inputs further increases the accuracy and evaluation efficiency compared to the conventional use of Bernoulli sequences. The proposed approach can further account for various fault models as well as calculating the soft error rate (SER).
报告题目2: Approximate Arithmetic Circuits and Their Applications
报告时间：2019年2月21日 下午 14:00-16:00
报告摘要：Often as the most important arithmetic modules in a processor, adders, multipliers and dividers determine the performance and energy efficiency of many computing tasks. The demand of higher speed and power efficiency, as well as the feature of error resilience in many applications (e.g., multimedia, recognition and data analytics), have driven the development of approximate arithmetic design. In this talk, a review and classification are presented for the current designs of approximate arithmetic circuits including adders, multipliers and dividers. A comprehensive and comparative evaluation of their error and circuit characteristics is performed for understanding the features of various designs. Image processing and cerebellar models are considered to show the effectiveness of the approximate arithmetic circuits in improving the energy efficiency and performance of these computation-intensive applications.
报告题目3: Stochastic Computing and Their Applications in Neural Network Design
报告时间：2019年2月22日 上午 9:00-11:00
报告摘要：Stochastic computing is a different paradigm that utilizes random binary bit streams to encode information for computation. In this talk, we provide an overview of our research on stochastic computation with a focus on neural network designs, including multilayer perceptron, deep belief networks and recurrent neural networks. The stochastic computational neural networks show higher energy efficiency and better noise tolerance than their conventional counterparts with little or no accuracy loss.